Posts by Bogdan Vukobratović
First instruction is probably going to be unlike any other in the amount of work that I’ll need to put into implementing it, so it deserves a post on its own. Let’s start from the RV32I description in the (currently) latest version of the RISC-V ISA Specification, which is given in the Chapter 2: RV32I Base Integer Instruction Set. The specification first goes on to describe Integer Computational Instructions (Chapter 2.4), of which the
addi instruction is explained first, so let’s start with that one.
Add support for user configuration
.pygears.py files that are loaded at startup. These files can be local to the project or located in
~/.pygears.py and active globally.
This post only explains the setup procedure for the additional tools needed for the RISC-V development. Installation procedure for the PyGears tools has been discussed in the previous post.
Add less-then ‘<’ operator
Welcome to the blog series in which I’ll be implementing the RISC-V ISA (Instruction Set Architecture) in hardware using functional approach with PyGears. My aim is to show how PyGears offers a way to build hardware in an incremental, evolutionary fashion, where the architecture, implementation and the verification environment evolve together, as opposed to the standard approach where these steps mostly happen in sequence. Developing hardware in such an agile way offers many benefits to the hardware design process, with some of them being that: